Originally introduced in 1994, low voltage differential signaling (LVDS) has now become commonly used for data transfer in products such as LCD TVs, automotive infotainment systems, industrial cameras, machine vision, notebook and tablet computers, and communications systems. Typical applications include high-speed video, graphics, video camera data transfers, space applications, and general purpose computer buses.
Since LVDS is a differential signaling system, it transmits information as the difference between the voltages on a pair of lines; these two line voltages are compared at a LVDS receiver receiving a LVDS signal. In a typical implementation, a LVDS transmitter injects a constant current into the lines, with the direction of current determining the logic level being communicated. The current passes through a termination resistor (matched to the cable's characteristic impedance to reduce reflections) at the receiving end, and then returns in the opposite direction via the other line. The LVDS receiver senses the polarity of the voltage across the resistor to determine the logic level being communicated. This provides for the transmission of binary data.
Shown in FIG. 1A is a waveform of typical operation of a pair of lines used in LVDS, with one line labeled as D+, and the other labeled as D−, switching about a common mode voltage Vcm. It can be seen that the logic levels of the lines D+ and D− are complementary.
The differential voltage VOD between the D+ and D− lines of FIG. 1A in operation can be seen in FIG. 1B, where it can be observed that the absolute value of the differential voltage VOD in this example is greater than a threshold of 100 mV (for most of the time) when the differential signals on the lines D+ and D− are arriving in a normal condition. As shown in FIG. 1C, in DC conditions, for the communication of a logic high, the D− line will have a voltage of Vcm-VOD/2, while the D+ line will have a voltage equal to Vcm+VOD/2. As shown in FIG. 1D, the differential voltage VOD is greater than a threshold of 100 mV. Similarly, for the communication of a logic low, the D− line will have a voltage of Vcm+VOD/2, while the D+ line will have a voltage of Vcm-VOD/2 V, meaning that the differential voltage VOD is less than a threshold of −100 mV.
Faults or failures with the D+ and D− lines may occur. Potential faults include both lines being open and disconnected from the transmitter, the lines being shorted and disconnected from the transmitter, the lines being shorted but connected to the transmitter, and one line being cut while the other line receives the signal.
When operation becomes abnormal in the presence of a fault, the voltages on the D− and D+ lines may be very close to each other in certain fault conditions, as shown in FIG. 1E, with the resulting differential voltage VOD being approximately 0 mV, as shown in FIG. 1F. This type of fault shown in FIGS. 1E-1F is where the lines D− or D+ have been shorted, or both lines are open.
An example of a fault in which one line is cut while the other continues to switch (with the switching frequency on the lines being high) is shown in FIG. 1G, where the D+ line is cut, but the D− line continues to switch. As can be seen, the voltage on the D+ follows that of the D− line, but with a delay, due to line capacitance and a terminal resistor of the line. Here in this example, the absolute value of VOD is never above a threshold of 100 mV, but it should be noted that this value can be higher in case the fault in line is located away from the receiver. Another example of a cut line fault would be there the D+ line is cut, but the D− line continues to switch, and the switching frequency on the lines is low, as shown in FIG. 1H. Here, it can be seen that the D+ line follows the D− line without delay, so VOD is zero.
From the fault conditions shown in FIGS. 1E-1H, it can be understood that faults on the lines D− and D+ can generally be determined where the absolute value of VOD is below a set threshold, with the possible exception of one line being cut and line switching speed being high (FIGS. 1G-1H). As a consequence, in the prior art it is known to use a window comparator to determine fault conditions. This window of normal operation and fault is depicted in FIG. 1I.
A circuit diagram for a prior art window comparator 1 is shown in FIG. 1J. Here, a first comparator 2 has its non-inverting terminal coupled to receive the D+ line through an offset (25 mV in this example), and has its inverting terminal coupled to receive the D− line. A second comparator 3 has its non-inverting terminal coupled to receive the D− line through the same offset value, and has its inverting terminal coupled to receive the D+ line. The output of the first comparator 2 is shown as OUT1, while the output of the second comparator 3 is shown as OUT2. The purpose of the offset is to set a threshold differentiating between a differential voltage VOD indicating normal operation and a differential voltage VOD indicating faulty operation. Here, the differential voltage VOD having an absolute value of less than the offset of 25 mV will be considered a faulty operation. In normal operation, one of the comparators 2 and 3 will output a logic high, and one will output a logic low, and these will switch when the voltage on the D+ and D− lines switches. In the presence of a fault, however, both comparators 2 and 3 will output a logic high due to the offsets (since VOD is below the threshold), and detection of a logic high from both comparators indicates error.
Normal operation of the window comparator 1 is shown in FIG. 1K. Here, the D+ and D− lines can be seen to be switching normally, with the absolute value of VOD being greater than 100 mV. This produces clean digital outputs OUT1 and OUT2 from the comparators 2 and 3, which clearly show the voltage levels communicated. This normal operation is at a lower frequency.
A fault condition where one line is cut at low frequency is now described with reference to FIG. 1L. Here, the D+ line has been cut, but the D− line continues to switch. Therefore, as explained, since the absolute value of VOD is zero, both OUT1 and OUT2 are pulled high. The window comparator 1 works well to detect faults, and the OUT1 and OUT2 values can be used to distinguish between fault and normal conditions by using suitable logical AND or exclusive-OR (XOR) digital gates.
A problem arises at higher frequencies, even under normal operating conditions. Shown in FIG. 1M is a scenario where the D+ and D− lines are properly switching at high frequency, with the absolute value of the differential voltage VOD being greater than a threshold of 100 mV. Unfortunately, these higher frequencies are outside the bandwidth of the comparators 2 and 3, resulting in the outputs OUT1 and OUT2 of the comparators 2 and 3 barely changing, and OUT1 and OUT2 effectively remaining pulled high. As a result, a test circuit reading the outputs OUT1 and OUT2 of the comparators 2 and 3 would erroneously assume improper operation of the LVDS system.
One attempt at designing a window comparison system that corrects these issues was made by Texas Instruments, described in a publication entitled “Active Fail-Safe in TI's LVDS Receivers”, by Mark Morgan and Bryan Smith, published in October 2001 (incorporated by reference).
A circuit diagram for this window comparison system 5 can be seen in FIG. 1N, and includes a main receiver 6 coupled to receive data from LVDS signals A and B. A window comparator 12 is included, and is comprised of comparators 7 and 8. The comparator 7 has the B line coupled to its non-inverting input and the A line coupled to its inverting input, while the comparator 8 has the A line coupled to its non-inverting input and the B line coupled to its inverting input. These comparators 7 and 8 have an offset of 80 mV, meaning that comparator 7 will pull its output high when the voltage on A is greater than the voltage of B by more than 80 mV, and the comparator 8 will pull its output high when the voltage on B is greater than the voltage on A by more than 80 mV. A NAND gate 10 receives the outputs from the comparators 7 and 8 and from the fail safe timer 9.
The fail safe timer 9 receives output from the main receiver 6. The fail safe timer 9 runs until it times out, but can be reset to continue to run (or to start running again if timed out) by toggling of the main receiver 6. While running, the fail safe timer 9 outputs a logic low. When the fail safe timer 9 times out, the output of the fail safe timer 9 is pulled high. Therefore, the purpose of the fail safe timer 9 is to mask the output signals from the comparators 7 and 8 as long as the receiver is toggling (since the output of the NAND gate 10 will be high regardless of the outputs of the comparators 7 and 8 if the output of the fail safe timer 9 is low), and to allow the NAND comparison of the output signals from the comparators 7 and 8 once the fail safe timer 9 has timed out (since the output of the NAND gate 10 will be a result of a NAND operation between the outputs of the comparators 7 and 8 if the output of the fail safe timer 9 is high).
NAND gate 11 receives the output of the main receiver 6 as input, as well as the output of the NAND gate 10. NAND gate 11 is not part of the fault detection, but uses the fault information provided by NAND gate 10 to selectively mask or unmask the output of the main receiver 6. If a fault is found to be present, after the fail safe timer 9 times out and pulls its output high, the NAND gate 10 pulls its output low (as its other inputs, the output of comparators 7 and 8, are by now settled to logic high owing to the fault condition), with the result being that the output of the NAND gate 11 will be high at all times. If a fault is not found to be present, the NAND gate 10 pulls its output high, with the result being that the output of the NAND gate 11 follows the output of the main receiver 6.
The window comparison system 5 has drawbacks and is not suitable in all situations. For example, the window comparison system 5 is reliant on the main receiver 6 operating properly. The main receiver 6 is also sensitive to external noise. If external noise is large enough to cause the main receiver 6 to switch (even in a fault conditions), the fail safe timer 9 is reset, and the fault detection provided by the window comparator 12 is kept disabled (masked by the NAND gate 10) until the input noise becomes insufficient to cause the main receiver 6 to switch for the entire period of the fail safe timer 9.
Therefore, further development on window comparison systems is needed so as to develop window comparison systems without these and other drawbacks.